Using make

When a program is composed of lots of sources files, it is much faster to keep the object files and recompile each source files only when needed. This can be automated using make. It executes a program written in a makefile, normally named Makefile. A sample makefile for the previous tutorial program could be :

Example 2-1A simple Makefile file
CC=gcc 	# the C compiler is gcc
CFLAGS=-g -Wall -I/usr/include/libxml2
tut_prog: main.o aux.o   # what we need to have 'tut_prog'...
	$(CC) $(LIBS) main.o aux.o -o tut_prog # ...and how to get it from the ingredients.
main.o: main.c
	$(CC) -c $(CFLAGS) main.c
aux.o: aux.c
	$(CC) -c $(CFLAGS) aux.c

Makefiles are a kind of program but instead of writing what should be done sequentially to get the result, you define some rules and make uses these rules in whatever order to achieve the result.

2.2.1. Variables

Like in any programming language, you can define variables in a make file. All variables contains a string or a list of strings separated by whitespace. A variable is defined using the following syntax: name=value. You can get its value by writing $(name) or ${name}. In the sample above, three variables are defined CC, CFLAGS and LIBS.

Variables can be redefined when calling make in the command line or using values from environment. Moreover make includes some default rules using predefined variables. Here is a list of the most common ones:


Program for compiling C programs, default 'cc'


Program for compiling C++ programs, default 'g++'


Program for running C preprocessor, default '$(CC) -E'


Program for running Fortran compiler, default 'f77'


Command to remove a file, default 'rm -f'


Extra flags for the C compiler


Extra flags for the C++ compiler


Extra flags for the C++ compiler


Extra flags for the C preprocessor


Extra flags for the Fortran compiler


Extra flags for the linker

2.2.2. Rules

The basic syntax for make rules is:

target: prerequisites

The target and the prerequisites are normally files but they could be actions. The rule is interpreted as in order to make the target or update it if it is older than its prerequisites, you need to make all prerequisites and then run all commands.

make starts with the first target of the makefile or the one given in the command line and looks for a rule. If this rules has no prerequisites, the associated commands are run and that's all. Else before running the commands, for each prerequisite, make looks for a rule having it as target and repeats the same process.

In the sample above, if you run make or make tut_prog. make does the following:

Search a rule with tut_prog as target
Found with prerequisites main.o aux.o
	Search a rule with main.o as target
	Found with prequisite main.c
		Search a rule with main.c as target
		Not found (main.c is a source file)
	If main.o does not exist or is older than main.c
		Compile main.c, do not link (-c switch)
	Search a rule with aux.o as target
	Found with prequisite aux.c
		Search a rule with aux.c as target
		Not found (aux.c is a source file)
	If aux.o does not exist or is older than aux.c
		Compile aux.c, do not link (-c switch)
If tut_prog is older than main.o or aux.o
	Link main.o, aux.o and libxml2

Like for variables, several target names are commonly defined:


Do everything


Perform some self test after building the program


Delete all files created by make


Delete more files than clean, could delete the Makefile itself


Create a distribution package, a compressed tarball by example


Install target created by make, need to be run as root to install in system directories


Remove files installed by make

Programs compiled from sources are installed by default in /usr/local. If you want to install (or uninstall) a program in such system directory, you normally need to log as root using su or sudo before running make install.